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| 2 A/3 A, 20 V, 700 kHz, Nonsynchronous Step-Down Regulators ADP2302/ADP2303 FEATURES Wide input voltage range: 3.0 V to 20 V Maximum load current 2 A for ADP2302 3 A for ADP2303 1.5% output accuracy over temperature Output voltage down to 0.8 V 700 kHz switching frequency Current-mode control architecture Automatic PFM/PWM mode Precision enable pin with hysteresis Integrated high-side MOSFET Integrated bootstrap diode Internal compensation and soft start Power-good output Undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) 8-lead SOIC package with exposed paddle VIN VIN BST TYPICAL APPLICATIONS CIRCUIT ADP2302/ ADP2303 PGOOD SW VOUT ON OFF EN GND FB 08833-001 Figure 1. Typical Application Circuit 100 90 EFFICIENCY (%) 80 70 APPLICATIONS Intermediate power rail conversion DC-to-DC point of load applications Communications and networking Industrial and instrumentation Healthcare and medical Consumer 60 50 VOUT = 3.3V INDUCTOR: VLF10040T-4R7N5R4 DIODE: SSB43L VOUT = 5.0V 40 OUTPUT CURRENT (A) Figure 2. ADP2303 Efficiency vs. Output Current at VIN = 12 V GENERAL DESCRIPTION The ADP2302/ADP2303 are fixed frequency, current-mode control, step-down, dc-to-dc regulators with an integrated power MOSFET. The ADP2302/ADP2303 can run from an input voltage of 3.0 V to 20 V, which makes them suitable for a wide range of applications. The output voltage of the ADP2302/ ADP2303 can be down to 0.8 V for the adjustable version, while the fixed output version is available in preset output voltage options of 5.0 V, 3.3 V, and 2.5 V. The 700 kHz operating frequency allows small inductor and ceramic capacitors to be used, providing a compact solution. Current mode control provides fast and stable line and load transient performance. The ADP2302/ADP2303 have integrated soft start circuitry to prevent a large inrush current at power-up. The power-good signal can be used to sequence devices that have an enable input. The precision enable threshold voltage allows the part to be easily sequenced from other input/output supplies. Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), thermal shutdown (TSD), and overcurrent protection (OCP). The ADP2302/ADP2303 devices are available in the 8-lead, SOIC package with exposed paddle and are rated for the -40oC to +125oC junction temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. 08833-002 0 0.5 1.0 1.5 2.0 2.5 3.0 ADP2302/ADP2303 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Typical Applications Circuit............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Functional Block Diagram ............................................................ 13 Theory of Operation ...................................................................... 14 Basic Operation .......................................................................... 14 PWM Mode................................................................................. 14 Power Saving Mode.................................................................... 14 Bootstrap Circuitry .................................................................... 14 Precision Enable ......................................................................... 14 Integrated Soft Start ................................................................... 14 Current Limit .............................................................................. 14 Short-Circuit Protection............................................................ 14 Undervoltage Lockout (UVLO) ............................................... 15 Thermal Shutdown (TSD)......................................................... 15 Overvoltage Protection (OVP)................................................. 15 Power Good ................................................................................ 15 Control Loop............................................................................... 15 Applications Information .............................................................. 16 Programming Output Voltage .................................................. 16 Voltage Conversion Limitations............................................... 16 Low Input Voltage Considerations .......................................... 17 Programming the Precision Enable ......................................... 17 Inductor ....................................................................................... 17 Catch Diode ................................................................................ 18 Input Capacitor........................................................................... 19 Output Capacitor........................................................................ 19 Thermal Consideration ............................................................. 19 Design Example .............................................................................. 20 Catch Diode Selection ............................................................... 20 Inductor Selection ...................................................................... 20 Output Capacitor Selection....................................................... 20 Resistive Voltage Divider Selection.......................................... 20 Circuit Board Layout Recommendations ................................... 22 Typical Application Circuits ......................................................... 23 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 REVISION HISTORY 7/10--Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADP2302/ADP2303 SPECIFICATIONS VIN = 3.3 V, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameters VIN Voltage Range Supply Current Shutdown Current Undervoltage Lockout Threshold FB Regulation Voltage Symbol VIN IVIN ISHDN UVLO Test Conditions Min 3.0 No switching, VIN = 12 V VEN = 0 V, VIN = 12 V VIN rising VIN falling ADP230xARDZ (adjustable) ADP230xARDZ-2.5 ADP230xARDZ-3.3 ADP230xARDZ-5.0 ADP230xARDZ (adjustable) VBST - VSW = 5 V, ISW = 200 mA ADP2302, VBST - VSW = 5 V ADP2303, VBST - VSW = 5 V VEN = VSW = 0 V, VIN = 12 V 720 24 2.7 2.4 0.8 2.5 3.3 5.0 0.01 120 3.5 5.5 0.1 126 210 700 2048 1.2 100 1.2 5.0 87.5 2.5 32 150 0.1 150 15 Typ Max 20 950 45 2.9 Unit V A A V V V V V V A m A A A ns ns kHz Clock cycles V mV A V % % Clock cycles mV A C C 2.2 0.788 2.463 3.25 4.925 VFB Bias Current SW On Resistance 1 Peak Current Limit Leakage Current Minimum On Time Minimum Off Time OSCILLATOR FREQUENCY SOFT START TIME EN Input Threshold Input Hysteresis Pull-Down Current BOOTSTRAP VOLTAGE PGOOD PGOOD Rising Threshold PGOOD Hysteresis PGOOD Deglitch Time 2 PGOOD Output Low Voltage PGOOD Leakage Current THERMAL SHUTDOWN Threshold Hysteresis 1 2 IFB 0.812 2.538 3.35 5.075 0.1 160 4.4 6.4 5 170 280 805 80 2.7 4.6 fSW 595 VEN 1.12 1.28 VBOOT VIN = 12 V 4.7 82.5 5.3 92.5 VPGOOD = 5 V Rising temperature 300 1 Pin-to-Pin measurements. Guaranteed by design. Rev. 0 | Page 3 of 28 ADP2302/ADP2303 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, EN, PGOOD SW BST to SW FB, NC Operating Junction Temperature Range Storage Temperature Range Soldering Conditions MAX Rating -0.3 V to +24 V -1.0 V to +24 V -0.6 V to +6 V -0.3 V to +6 V -40C to +125C -65C to +150C JEDEC J-STD-020 THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance1 Package Type 8-Lead SOIC_N_EP 1 JA 58.5 Unit C/W JA is measured using natural convection on JEDEC 4-layer board. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to GND. Rev. 0 | Page 4 of 28 ADP2302/ADP2303 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BST 1 VIN 2 EN 3 ADP2302 ADP2303 8 7 6 5 SW GND NC FB TOP VIEW PGOOD 4 (Not to Scale) Figure 3. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 (EPAD) Mnemonic BST VIN EN PGOOD FB NC GND SW Exposed Pad Description Bootstrap Supply for the High-Side MOSFET Driver. A 0.1 F capacitor is connected between SW and BST to provide a floating driver voltage for the power switch. Power Input. Connect to the input power source with a ceramic bypass capacitor to GND directly from this pin. Output Enable. Pull this pin high to enable the output. Pull this pin low to disable the output. This pin can also be used as a programmable UVLO input. This pin has an internal 1.2 A pull-down current to GND. Power-Good Open-Drain Output. Feedback Voltage Sense Input. For the adjustable version, connect this pin to a resistive divider from VOUT. For the fixed output version, connect this pin to VOUT directly. Used for internal testing. Connect to GND or leave this pin floating to ensure proper operation. Ground. Connect this pin to the ground plane. Switch Node Output. Connect an inductor to VOUT and a catch diode to GND from this pin. The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation. Rev. 0 | Page 5 of 28 08833-003 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. ADP2302/ADP2303 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3 V, TA = 25C, unless otherwise noted. 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) 80 80 70 70 VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V INDUCTOR: VLF10040T-4R7N5R4 DIODE: SSB43L 0 0.5 1.0 1.5 2.0 2.5 3.0 08833-007 60 VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 60 50 INDUCTOR: VLF10040T-6R8N4R5 DIODE: SSB43L 0 0.5 1.0 1.5 2.0 2.5 3.0 08833-004 50 40 40 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 4. ADP2303 Efficiency, VIN = 18 V 100 100 Figure 7. ADP2303 Efficiency, VIN = 12 V 90 90 EFFICIENCY (%) EFFICIENCY (%) 80 80 70 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V INDUCTOR: VLF10040T-2R2N7R1 DIODE: SSB43L 0 0.5 1.0 1.5 2.0 2.5 3.0 08833-005 70 VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 60 60 50 50 INDUCTOR: VLF10040T-6R8N4R5 DIODE: SSB43L 0 0.5 1.0 OUTPUT CURRENT (A) 1.5 2.0 08833-008 40 OUTPUT CURRENT (A) 40 Figure 5. ADP2303 Efficiency, VIN = 5 V 100 Figure 8. ADP2302 Efficiency, VIN = 18 V 100 90 90 EFFICIENCY (%) 70 EFFICIENCY (%) 80 80 70 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 60 VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V INDUCTOR: VLF10040T-6R8N4R5 DIODE: SSB43L 0 0.5 1.0 OUTPUT CURRENT (A) 1.5 2.0 08833-006 60 50 50 INDUCTOR: VLF10040T-3R3N6R2 DIODE: SSB43L 0 0.5 1.0 OUTPUT CURRENT (A) 1.5 2.0 08833-009 40 40 Figure 6. ADP2302 Efficiency, VIN = 12 V Figure 9. ADP2302 Efficiency, VIN = 5 V Rev. 0 | Page 6 of 28 ADP2302/ADP2303 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 08833-010 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 08833-013 -0.20 5 8 11 VIN (V) 14 17 20 LOAD REGULATION (%) LINE REGULATION (%) -0.20 0 0.5 1.0 OUTPUT CURRENT (A) 1.5 2.0 Figure 10. ADP2302 Line Regulation, VOUT = 3.3 V, IOUT = 2 A 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 08833-011 Figure 13. ADP2302 Load Regulation, VOUT = 3.3V, VIN = 12 V 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 08833-014 -0.20 5 8 11 VIN (V) 14 17 20 LOAD REGULATION (%) LINE REGULATION (%) -0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) Figure 11. ADP2303 Line Regulation, VOUT = 3.3 V , IOUT = 3 A Figure 14. ADP2303 Load Regulation, VOUT = 3.3 V, VIN = 12 V 50 45 SHUTDOWN CURRENT (A) QUIESCENT CURRENT (A) 900 850 800 750 700 650 600 550 500 TJ = -40C TJ = +25C TJ = +125C 40 35 30 25 20 15 10 5 0 TJ = -40C TJ = +25C TJ = +125C 08833-012 2 4 6 8 10 12 14 16 18 20 2 4 6 8 VIN (V) 10 12 VIN (V) 14 16 18 20 Figure 12. Shutdown Current vs. VIN Figure 15. Quiescent Current vs. VIN Rev. 0 | Page 7 of 28 08833-015 ADP2302/ADP2303 810 790 770 812 810 808 FEEDBACK VOLTAGE (mV) 08833-016 750 FREQUENCY (kHz) 730 710 690 670 650 630 610 590 -40 -20 0 20 40 60 80 100 120 806 804 802 800 798 796 794 792 790 -20 0 20 40 60 80 100 120 08833-019 08833-021 788 -40 TEMPERATURE (C) TEMPERATURE (C) Figure 16. Frequency vs. Temperature 4.4 4.2 Figure 19. 0.8 V Feedback Voltage vs. Temperature 6.4 6.2 PEAK CURRENT LIMIT (A) PEAK CURRENT LIMIT (A) 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 -40 6.0 5.8 5.6 5.4 5.2 5.0 4.8 -20 0 20 40 60 80 100 120 08833-017 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) Figure 17. ADP2302 Current-Limit Threshold vs. Temperature, VBST - VSW = 5 V 2.9 2.8 Figure 20. ADP2303 Current-Limit Threshold vs. Temperature, VBST - VSW = 5 V 1.30 1.25 ENABLE THRESHOLD (V) UVLO THRESHOLD (V) 2.7 RISING 2.6 2.5 2.4 FALLING 2.3 2.2 -40 RISING 1.20 1.15 FALLING 1.10 1.05 -20 0 20 40 60 80 100 120 08833-018 1.00 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) Figure 18. UVLO Threshold vs. Temperature Figure 21. Enable Threshold vs. Temperature Rev. 0 | Page 8 of 28 08833-020 4.6 -40 ADP2302/ADP2303 270 265 260 255 150 145 140 MINIMUM OFF TIME (ns) MINIMUM ON TIME (ns) 08833-022 250 245 240 235 230 225 220 215 210 205 -40 -20 0 20 40 60 80 100 120 135 130 125 120 115 110 105 08833-025 100 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) Figure 22. Minimum Off Time vs. Temperature Figure 25. Minimum On Time vs. Temperature 180 170 160 VOUT (AC) 1 MOSFET RESISTOR (m) 150 140 130 120 110 100 90 80 70 08833-023 IL SW 4 VGS = 3V VGS = 4V VGS = 5V 2 -20 0 20 40 60 80 100 120 CH1 5.00mV B W TEMPERATURE (C) CH2 5.00V M1.00s CH4 2.00A T 30.00% A CH2 7.50V Figure 23. MOSFET RDSON vs. Temperature (Pin-to-Pin Measurement) Figure 26. Continuous Conduction Mode (CCM), VOUT = 3.3 V, VIN = 12 V VOUT (AC) 1 VOUT (AC) IL 4 1 4 IL SW SW 2 2 08833-024 CH1 5.00mV B W CH2 5.00V M1.00s CH4 2.00A T 30.00% A CH2 7.50V CH1 50.00mV B W CH2 5.00V CH4 2.00A M200s A CH2 T 30.00% 7.50V Figure 24. Discontinuous Conduction Mode (DCM), VOUT = 3.3 V, VIN = 12 V Figure 27. Power Saving Mode, VOUT = 3.3 V, VIN = 12 V Rev. 0 | Page 9 of 28 08833-027 08833-026 60 -40 ADP2302/ADP2303 VOUT VOUT 1 IL 1 IL 4 4 EN SW 3 EN SW 3 2 2 08833-028 CH1 2.00V BW CH3 10.0V BW CH2 10.0V M1.00ms CH4 2.00A T 20.20% A CH3 6.20V CH1 2.00V BW CH3 10.0V BW CH2 10.0V M1.00ms CH4 2.00A T 20.20% A CH3 3.60V Figure 28. Soft Start Without Load, VOUT = 3.3 V, VIN = 12 V Figure 31. Soft Start with Full Load, VOUT = 3.3 V, VIN = 12 V VOUT (AC) 1 1 VOUT (AC) IO IO 4 4 08833-029 CH1 500mV B W CH4 2.00A M200s T 20.00% A CH4 1.20A CH1 200mV B W CH4 2.00A M200s T 20.00% A CH4 1.88A Figure 29. ADP2303 Load Transient, 0.5 A to 3.0 A, VOUT = 5.0 V, VIN = 12 V, L = 4.7 H, COUT = 47 F Figure 32. ADP2303 Load Transient, 0.5 A to 3.0 A, VOUT = 3.3 V, VIN = 12 V, L = 4.7 H, COUT = 2 x 47 F VOUT (AC) 1 1 VOUT (AC) IO IO 4 4 08833-030 08833-032 08833-031 CH1 200mV B W CH4 1.00A M200s T 20.00% A CH4 1.20A CH1 200mV B W CH4 1.00A M200s T 20.00% A CH4 1.20A Figure 30. ADP2302 Load Transient, 0.5 A to 2.0 A, VOUT = 5.0 V, VIN = 12 V, L = 6.8 H, COUT = 2 x 22 F Figure 33. ADP2302 Load Transient, 0.5 A to 2.0 A, VOUT = 3.3 V, VIN = 12 V, L = 6.8 H, COUT = 2 x 22 F Rev. 0 | Page 10 of 28 08833-033 ADP2302/ADP2303 VOUT VOUT 1 1 IL IL 4 SW 4 SW 2 08833-034 2 CH1 1.00mV B W CH2 10.0V M40.0s CH4 5.00A T 30.00% A CH1 1.26V CH1 1.00V B W CH2 10.0V M400s CH4 5.00A T 30.00% A CH1 1.26V Figure 34. Output Short, VOUT = 3.3 V, VIN = 12 V, L = 4.7 H, COUT = 2 x 47 F Figure 37. Output Short Recovery, VOUT = 3.3 V, VIN = 12 V, L = 4.7 H, COUT = 2 x 47 F VOUT 1 VOUT VIN VIN 1 SW SW 3 3 2 2 08833-035 08833-037 CH1 20.0mV BW CH2 10.0V BW CH3 5.00V BW M1.00ms A CH3 T 23.40% 11.0V CH1 20.0mV BW CH2 10.0V BW M1.00ms CH3 5.00V BW T 23.40% A CH3 11.0V Figure 35. ADP2303 Line Transient, 7 V to 15 V, VOUT = 3.3 V, IOUT = 3 A, L = 4.7 H, COUT = 2 x 47 F 80 64 48 32 MAGNITUDE (dB) Figure 38. ADP2302 Line Transient, 7 V to 15 V, VOUT = 3.3 V, IOUT = 2 A, L = 6.8 H, COUT = 2 x 22 F 80 64 48 32 180 144 108 72 36 0 -36 -72 -108 CROSS FREQUENCY = 42kHz PHASE MARGIN = 56 1k 10k 100k FREQUENCY (Hz) 1M -144 08833-039 180 144 108 72 MAGNITUDE (dB) 16 0 -16 -32 -48 -64 -80 1k CROSS FREQUENCY = 36kHz PHASE MARGIN = 60 36 0 -36 -72 -108 -144 PHASE (Degrees) 16 0 -16 -32 -48 -64 08833-036 -180 10k 100k FREQUENCY (Hz) 1M -80 -180 Figure 36. ADP2302 Bode Plot, VOUT = 2.5 V, VIN = 12 V, L = 4.7 H, COUT =3 x 22 F Figure 39. ADP2302 Bode Plot, VOUT = 3.3 V, VIN = 12 V, L = 6.8 H, COUT = 2 x 22 F Rev. 0 | Page 11 of 28 PHASE (Degrees) 08833-038 ADP2302/ADP2303 80 64 48 32 180 144 108 80 64 48 MAGNITUDE (B/A) (dB) 180 144 108 PHASE (B-A) (Degeres) PHASE (B-A) (Degeres) 08833-143 08833-142 72 36 0 -36 -72 -108 CROSS FREQUENCY = 32kHz PHASE MARGIN = 59 1k 10k 100k FREQUENCY (Hz) 1M -144 08833-040 32 16 0 -16 -32 -48 -64 -80 1k CROSS FREQUENCY = 26kHz PHASE MARGIN = 65 72 36 0 -36 -72 -108 -144 -180 10k 100k FREQUENCY (Hz) 1M MAGNITUDE (dB) 16 0 -16 -32 -48 -64 -80 -180 Figure 40. ADP2302 Bode Plot, VOUT = 5 V, VIN = 12 V, L = 6.8 H, COUT = 2 x 22 F 80 64 48 32 180 144 108 PHASE (Degrees) Figure 42. ADP2303 Bode Plot, VOUT = 2.5 V, VIN = 12 V, L = 3.3 H, COUT = 2 x 47 F 80 64 48 MAGNITUDE (B/A) (dB) 32 16 0 -16 -32 -48 -64 08833-041 180 144 108 72 36 0 -36 -72 -108 CROSS FREQUENCY = 28kHz PHASE MARGIN = 65 1k 10k 100k FREQUENCY (Hz) 1M -144 -180 72 36 0 -36 -72 -108 CROSS FREQUENCY = 19kHz PHASE MARGIN = 59 1k 10k 100k FREQUENCY (Hz) 1M -144 -180 MAGNITUDE (dB) 16 0 -16 -32 -48 -64 -80 PHASE (Degrees) -80 Figure 41. ADP2303 Bode Plot, VOUT = 3.3 V, VIN = 12 V, L = 4.7 H, COUT = 2 x 47 F Figure 43. ADP2303 Bode Plot, VOUT = 5 V, VIN = 12 V, L = 4.7 H, COUT = 47 F Rev. 0 | Page 12 of 28 ADP2302/ADP2303 FUNCTIONAL BLOCK DIAGRAM VIN VIN 2 THERMAL SHUTDOWN SHUTDOWN LOGIC UVLO SHUTDOWN IC 1.20V ON OFF EN 3 1.2A OVP 0.880V CURRENT LIMIT THRESHOLD OCP CURRENT SENSE AMPLIFIER BOOT REGULATOR R S PGOOD 4 VBIAS = 1.1V RAMP GENERATOR CLK GENERATOR 8 1 BST Q VOUT SW 0.680V FREQUENCY FOLDBACK ( fSW, 1/4 fSW, 1/2 fSW, fSW) NC 6 gm 5 0.8V VOLTAGE REFERENCE FB ADP2302/ADP2303 7 GND Figure 44. Functional Block Diagram Rev. 0 | Page 13 of 28 08833-042 ADP2302/ADP2303 THEORY OF OPERATION The ADP2302/ADP2303 are nonsynchronous, step-down, dc-to-dc regulators, each with an integrated high-side power MOSFET. The high switching frequency and 8-lead SOIC package provide a small, step-down, dc-to-dc regulator solution. The ADP2302/ADP2303 can operate with an input voltage from 3.0 V to 20 V while regulating an output voltage down to 0.8 V. The ADP2302 can provide 2 A maximum continuous output current, and the ADP2303 can provide 3 A maximum continuous output current. Because the output voltage occasionally dips below regulation and then recovers, the output voltage ripple in the power saving mode is larger than the ripple in the PWM mode of operation. BOOTSTRAP CIRCUITRY The ADP2302/ADP2303 each have an integrated boot regulator, which requires that a 0.1 F ceramic capacitor (X5R or X7R) be placed between the BST and SW pins to provide the gate drive voltage for the high-side MOSFET. There is at least a 1.2 V difference between the BST and SW pins to turn on the high-side MOSFET. This voltage should not exceed 5.5 V in case the BST pin is supplied with the external voltage source through a diode. The ADP2302/ADP2303 generate a typical 5.0 V bootstrap voltage for the gate drive circuit by differentially sensing and regulating the voltage between the BST and SW pins. There is a diode integrated on the chip that blocks the reverse voltage between the VIN and BST pins when the MOSFET switch is turned on. BASIC OPERATION The ADP2302/ADP2303 use the fixed-frequency, peak currentmode PWM control architecture from medium to high loads, but shift to a pulse-skip mode control scheme at light loads to reduce the switching power losses and improve efficiency. When these devices operate in fixed-frequency PWM mode, output regulation is achieved by controlling the duty cycle of the integrated MOSFET. While the devices are operating in pulse-skip mode at light loads, the output voltage is controlled in a hysteretic manner with higher output ripple. In this mode of operation, the regulator periodically stops switching for a few cycles, thus keeping the conversion losses minimal to improve efficiency. PRECISION ENABLE The ADP2302/ADP2303 provide a precision enable circuit that has 1.2 V reference threshold with 100 mV hysteresis. When the voltage at the EN pin is greater than 1.2 V (typical), the part is enabled. If the EN voltage falls below 1.1 V (typical), the chip is disabled. The precision enable threshold voltage allows the ADP2302/ADP2303 to be easily sequenced from other input/ output supplies. It also can be used as a programmable UVLO input by using a resistive divider. An internal 1.2 A pull-down current prevents errors if the EN pin is left floating. PWM MODE In PWM mode, the ADP2302/ADP2303 operate at a fixed frequency, set by an internal oscillator. At the start of each oscillator cycle, the MOSFET switch is turned on, providing a positive voltage across the inductor. The inductor current increases until the current-sense signal crosses the peak inductor current threshold that turns off the MOSFET switch; this threshold is set by the error amplifier output. During the MOSFET off time, the inductor current declines through the external diode until the next oscillator clock pulse comes and a new cycle starts. INTEGRATED SOFT START The ADP2302/ADP2303 have an internal digital soft start circuitry to limit the output voltage rise time and reduce the inrush current at power up. The soft start time is fixed at 2048 clock cycles. CURRENT LIMIT The ADP2302/ADP2303 include current-limit protection circuitry to limit the amount of positive current flowing through the highside MOSFET switch. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. POWER SAVING MODE To achieve higher efficiency, the ADP2302/ADP2303 smoothly transition to the pulse-skip mode when the output load decreases below the pulse-skip current threshold. When the output voltage dips below the regulation, the ADP2302/ADP2303 enter PWM mode for a few oscillator cycles until the voltage increases to regulation range. During the idle time between bursts, the MOSFET switch is turned off, and the output capacitor supplies all the output current. Because the pulse-skip mode comparator monitors the internal compensation node, which represents the peak inductor current information, the average pulse-skip load current threshold depends on the input voltage (VIN), the output voltage (VOUT), the inductor, and the output capacitor. SHORT-CIRCUIT PROTECTION The ADP2302/ADP2303 include frequency foldback to prevent output current runaway when there is a hard short on the output. The switching frequency is reduced when the voltage at the FB pin drops below a certain value, which allows more time for the inductor current to decline, but increases the ripple current while regulating the peak current. This results in a reduction in average output current and prevents output current runaway. The correlation between the switching frequency and the FB pin voltage is shown in Table 5. Rev. 0 | Page 14 of 28 ADP2302/ADP2303 Table 5. Correlation Between fSW and VFB FB Pin Voltage VFB 0.6 V 0.4 V < VFB < 0.6 V 0.2 V < VFB 0.4 V VFB 0.2 V Switching Frequency fSW 1/2 fSW 1/4 fSW 1/8 fSW OVERVOLTAGE PROTECTION (OVP) The ADP2302/ADP2303 provide an overvoltage protection feature to protect the system against an output short to a higher voltage supply. If the feedback voltage is above 0.880 V, the internal high-side MOSFET is turned off, until the voltage at FB decreases to 0.850 V. At that time, the ADP2302/ADP2303 resume normal operation. When a hard short (VFB 0.2 V) is removed, a soft start cycle is initiated to regulate the output back to its level during normal operation, which helps to limit the inrush current and prevent possible overshoot on the output voltage. POWER GOOD The PGOOD pin is an active high, open-drain output and requires a resistor to pull it up to a voltage (<20.0 V). A high indicates that the voltage on the FB pin (and therefore the output voltage) is above 87.5% of the reference voltage. A low indicates that the voltage on the FB pin is below 85% of the reference voltage. There is a 32-cycle waiting period after FB is detected as being in or out of bounds. UNDERVOLTAGE LOCKOUT (UVLO) The ADP2302/ADP2303 have fixed, internally set undervoltage lockout circuitry (UVLO). If the input voltage drops below 2.4 V, the ADP2302/ADP2303 shut down and the MOSFET switch turns off. After the voltage rises above 2.7 V, the soft start period is initiated, and the part is enabled. CONTROL LOOP The ADP2302/ADP2303 are internally compensated to minimize external component count and cost. In addition, the built-in slope compensation helps to prevent subharmonic oscillations when the ADP2302/ADP2303 operate at a duty cycle greater than or close to 50%. THERMAL SHUTDOWN (TSD) If the ADP2302/ADP2303 junction temperature rises above 150C, the thermal shutdown circuit disables the chip. Extreme junction temperature can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15C hysteresis is included so that when thermal shutdown occurs, the ADP2302/ADP2303 do not return to operation until the onchip temperature drops below 135C. When the devices recover from thermal shutdown, a soft start is initiated. Rev. 0 | Page 15 of 28 ADP2302/ADP2303 APPLICATIONS INFORMATION PROGRAMMING OUTPUT VOLTAGE ADP2302/ADP2303 have an adjustable version where the output voltage is programmed through an external resistive divider, as shown in Figure 45. Suggested resistor values for the typical output voltage setting are listed in Table 6. The output voltages are calculated using the following equation: R VOUT = 0.800 V x 1 + TOP R BOT The upper limit of the output voltage is constrained by the minimum controllable off time, which can be as high as 280 ns in ADP2302/ADP2303 for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the upper limit of the output voltage is VOUT(max) = tMIN-OFF x fSW(max) x (VIN(min) + VD) - VD where: VIN(min) is the minimum input voltage. fSW(max) is the maximum switching frequency for the worst case. VD is the diode forward drop. tMIN-OFF is the minimum controllable off time. In addition, the bootstrap circuit limits the minimum input voltage for the desired output due to the internal dropout voltage. To attain stable operation at light loads and ensure proper startup for the prebiased condition, the ADP2302/ADP2303 require the voltage difference between the input voltage and the regulated output voltage (or between the input voltage and the prebias voltage) to be greater than 2.1 V for the worst case. If the voltage difference is smaller, the bootstrap circuit relies on some minimum load current to charge the boost capacitor for startup. Figure 46 shows the typical required minimum input voltage vs. load current for the 3.3 V output voltage. 5.3 FOR START UP 5.1 4.9 4.7 VIN (V) where: VOUT is the output voltage. RTOP is the feedback resistor from VOUT to FB. RBOT is the feedback resistor from FB to GND. ADP2302/ ADP2303 RTOP FB RBOT VOUT Figure 45. Programming the Output Voltage Using a Resistive Voltage Divider Table 6. Suggested Values for Resistive Voltage Divider VOUT (V) 1.2 1.5 1.8 2.5 3.3 5.0 RTOP (k), 1% 10 10 12.7 21.5 31.6 52.3 RBOT (k), 1% 20 11.3 10.2 10.2 10.2 10 08833-043 4.5 4.3 4.1 3.9 3.7 08833-146 VOLTAGE CONVERSION LIMITATIONS There are both lower and upper output voltage limitations for a given input voltage due to the minimum on time, the minimum off time, and the bootstrap dropout voltage. The lower limit of the output voltage is constrained by the controllable minimum on time, which can be as high as 170 ns for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the lower limit of the output voltage is VOUT(min) = tMIN-ON x fSW(max) x (VIN(max) + VD) - VD where: VIN(max) is the maximum input voltage. fSW(max) is the maximum switching frequency for the worst case. tMIN-ON is the minimum controllable on time. VD is the diode forward drop. WHILE IN OPERATION 3.5 1 10 100 1000 OUPTUT CURRENT (mA) Figure 46. Minimum Input Voltage vs. Load Current Based on three conversion limitations (the minimum on time, the minimum off time, and the bootstrap dropout voltage), Figure 47 shows the voltage conversion limitations. Rev. 0 | Page 16 of 28 ADP2302/ADP2303 22 20 MAXIMUM INPUT VOLTAGE VIN VIN 18 16 14 VIN (V) REN1 ADP2302/ ADP2303 EN 08833-047 12 10 8 6 MINIMUM INPUT VOLTAGE REN2 Figure 49. Precision Enable Used as a Programmable UVLO 4 08833-147 2 0 2 4 6 8 VOUT (V) 10 12 14 16 The precision enable feature also allows the ADP2302/ADP2303 to be sequenced precisely by using a resistive voltage divider from another dc-to-dc power supply, as shown in Figure 50. Figure 47. Voltage Conversion Limitations LOW INPUT VOLTAGE CONSIDERATIONS For low input voltage between 3 V and 5 V, the internal boot regulator cannot provide enough bootstrap voltage due to the internal dropout voltage. As a result, the increased MOSFET RDS(ON) reduces the available load current. To prevent this, add an external small-signal Schottky diode from a 5.0 V external bootstrap bias voltage. Because the absolute maximum rating between the BST and SW pins is 6.0 V, the bias voltage should be less than 5.5 V. Figure 48 shows the application diagram for the external bootstrap circuit. 3.0V ~ 5.0V VIN BST 5V BIAS VOLTAGE SCHOTTKY DIODE ADP2302/ ADP2303 ANOTHER DC/DC SUPPLIER REN1 REN2 EN 08833-048 Figure 50. Precision Enable Used as a Sequencing Control from Another DC-to-DC Power Supply With a 1.2 A pull-down current on the EN pin, the equation for the start-up voltage in Figure 49 and Figure 50 is ADP2302/ ADP2303 SW 1.2 V VSTARTUP = + 1.2 A x R EN1 + 1.2 V R EN2 where: VSTARTUP is the start-up voltage to enable the chip. REN1 is the resistor from the dc source to EN. REN2 is the resistor from EN to GND. 08833-046 ON OFF EN GND FB INDUCTOR The high switching frequency of the ADP2302/ADP2303 allows the use of small inductors. For best performance, use inductor values between 1 H and 15 H. The peak-to-peak inductor ripple current is calculated using the following equation: Figure 48. External Bootstrap Circuit for Low Input Voltage Application PROGRAMMING THE PRECISION ENABLE Generally, the EN pin can connect to the VIN pin so that the device automatically starts up when the input power is applied. However, the precision enabling feature allows the ADP2302/ ADP2303 to be used as a programmable UVLO by connecting a resistive voltage divider to VIN, as shown in Figure 49. This configuration prevents the start-up problems that can occur when VIN ramps up slowly in soft start with a relatively high load current. I RIPPLE = (VIN - VOUT ) VOUT + VD x V +V L x f sw D IN where: fSW is the switching frequency. L is the inductor value. VD is the diode forward drop. VIN is the input voltage. VOUT is the output voltage. Inductors of smaller values are usually smaller in size but increase the ripple current and the output ripple voltage. As a guideline, the inductor peak-to-peak ripple current is typically set to 30% of the maximum load current for optimal transient Rev. 0 | Page 17 of 28 ADP2302/ADP2303 response and efficiency. Therefore, the inductor value is calculated using the following equation: L= CATCH DIODE The catch diode conducts the inductor current during the off time of the internal MOSFET. The average current of the diode in normal operation is, therefore, dependent on the duty cycle of the regulator as well as the output load current. V + VD I DIODE( AVG ) = 1 - OUT V IN + V D x I LOAD(max) (VIN - VOUT ) 0.3 x I LOAD (max) x f sw V + VD x OUT V +V D IN where ILOAD(max) is the maximum load current. The inductor peak current is calculated using the following equation: I PEAK = I LOAD (max) + I RIPPLE 2 where VD is the diode forward drop. The only reason to select a diode with a higher current rating than necessary in normal operation is for the worst-case condition, in which there is a shorted output. In this case, the diode current increases up to the typical peak current limit threshold. Be sure to consult the diode data sheet to ensure that the diode can operate well within the thermal and electrical limits. The reverse breakdown voltage rating of the diode must be higher than the highest input voltage and allow an appropriate margin for the ringing that may be present on the SW node. A Schottky diode is recommended for the best efficiency because it has a low forward voltage drop and fast switching speed. Table 7 provides a list of recommended Schottky diodes. Table 7. Recommended Schottky Diodes Vendor Vishay ON Semiconductor Diodes Inc. Part No. SSB43L SSA33L MBRS330T3 B330B VRRM (V) 30 30 30 30 IAVG (A) 4 3 3 3 The minimum current rating of the inductor must be greater than the inductor peak current. For ferrite core inductors with a quick saturation characteristic, the inductor saturation current rating should be higher than the switch current limit threshold to prevent the inductor from reaching its saturation point. Be sure to validate the worst-case condition, in which there is a shorted output, over the intended temperature range. Inductor conduction loss is caused by the flow of current through internal dc resistance (DCR). Larger sized inductors have smaller DCR of the inductor and, therefore, may reduce inductor conduction losses. Inductor core loss is related to the core material and the ac flux swing, which are affected by the peak-to-peak inductor ripple current. Because the ADP2302/ ADP2303 are high frequency switching regulators, shielded ferrite core materials are recommended for their low core losses and low EMI. Some recommended inductors are shown in Table 8. Table 8. Recommended Inductors Vendor Sumida Value (H) 2.5 3.8 5.2 7 10 2.5 3.8 5.2 7 10 2.8 3.7 4.7 6.4 10 2.2 3.3 4.7 6.8 10 Part No. CDRH104RNP-2R5N CDRH104RNP-3R8N CDRH104RNP-5R2N CDRH104RNP-7R0N CDRH104RNP-100N MSS1038-252NL MSS1038-382NL MSS1038-522NL MSS1038-702NL MSS1038103NL #919AS-2R8M #919AS-3R7M #919AS-4R7M #919AS-6R4M #919AS-100M VLF10040T-2R2N7R1 VLF10040T-3R3N6R2 VLF10040T-4R7N5R4 VLF10040T-6R8N4R5 VLF10040T-100M3R8 DCR (m) 7.8 9.6 16 20 26 10 13 22 27 35 10.7 14.2 16.2 22.9 26.5 7.9 10.5 12.7 19.8 28 ISAT (A) 7.5 6 5.5 4.8 4.4 7.62 6.5 5.28 4.74 3.9 8.3 7 6.1 5.2 4.3 8.2 6.7 5.4 4.6 3.8 Dimensions L x W x H (mm) 10.5 x 10.3 x 3.8 10.5 x 10.3 x 3.8 10.5 x 10.3 x 3.8 10.5 x 10.3 x 3.8 10.5 x 10.3 x 3.8 10 x 10.2 x 3.8 10 x 10.2 x 3.8 10 x 10.2 x 3.8 10 x 10.2 x 3.8 10 x 10.2 x 3.8 10.3 x 10.3 x 4.5 10.3 x 10.3 x 4.5 10.3 x 10.3 x 4.5 10.3 x 10.3 x 4.5 10.3 x 10.3 x 4.5 10 x 9.7 x 4.0 10 x 9.7 x 4.0 10 x 9.7 x 4.0 10 x 9.7 x 4.0 10 x 9.7 x 4.0 Coilcraft Toko TDK Rev. 0 | Page 18 of 28 ADP2302/ADP2303 INPUT CAPACITOR The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. The rms ripple current flowing through the input capacitor is, at maximum, ILOAD(max)/2. Select an input capacitor capable of withstanding the rms ripple current for an application's maximum load current using the following equation: coefficients. Y5V and Z5U dielectrics are not recommended because of their poor temperature and dc bias characteristics. In general, most applications require a minimum output capacitor value of 2 x 22 F. Some recommended output capacitors for VOUT 5.0 V are provided in Table 9. I IN ( RMS) = I LOAD(max) x D x (1 - D ) where D is the duty cycle and is equal to THERMAL CONSIDERATION ADP2302/ADP2303 have an internal high-side MOSFET and its drive circuit. Only a small amount of power dissipates inside the ADP2302/ADP2303 package under typical load conditions, which reduces thermal constraints. However, in applications with maximum loads at high ambient temperature and high duty cycle, the heat dissipated in the package may cause the junction temperature of the die to exceed the maximum junction temperature of 125C. If the junction temperature exceeds 150C, the regulator goes into thermal shutdown and recovers when the junction temperature drops below 135C. The junction temperature of the die is the sum of the ambient temperature and the temperature rise of the package due to power dissipation, as indicated in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rising temperature of the package due to power dissipation. The rising temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = JA x PD where: TR is the rising temperature of the package. JA is the thermal resistance from the junction of the die to the ambient temperature of the package. PD is the power dissipation in the package. D= VOUT + VD V IN + VD The recommended input capacitance is ceramic with X5R or X7R dielectrics due to its low ESR and small temperature coefficients. A capacitance of 10 F should be adequate for most applications. To minimize supply noise, place the input capacitor as close as possible to the VIN pin of the ADP2302/ADP2303. OUTPUT CAPACITOR The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. The ADP2302/ADP2303 are designed to operate with small ceramic capacitors that have low ESR and equivalent series inductance (ESL) and are, therefore, easily able to meet stringent output voltage ripple specifications. When the regulator operates in continuous conduction mode, the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor equivalent series resistance (ESR) plus the voltage ripple caused by the charging and discharging of the output capacitor 1 V RIPPLE = I RIPPLE x + ESR COUT 8x f xC sw OUT Capacitors with lower ESR are preferable to guarantee low output voltage ripple, as shown in the following equation: ESRCout VRIPPLE I RIPPLE Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. X5R or X7R dielectrics are recommended for best performance, due to their low ESR and small temperature Table 9. Recommended Capacitors for VOUT 5.0 V Vendor Murata TDK Value 22 F, 6.3 V, X5R 47 F, 6.3 V, X5R 22 F, 6.3 V, X5R 33 F, 6.3 V, X5R 47 F, 6.3 V, X5R Part No. GRM31CR60J226KE19 GRM32ER60J476ME20 C3216X5R0J226MB C3216X5R0J336MB C3225X5R0J476MB Dimensions L x W x H (mm) 3.2 x 2.5 x 2.0 3.2 x 2.5 x 2.0 3.2 x 1.6 x 0.85 3.2 x 1.6 x 1.3 3.2 x 2.5 x 2.5 Rev. 0 | Page 19 of 28 ADP2302/ADP2303 DESIGN EXAMPLE This section provides the procedures to select the external components, based on the example specifications listed in Table 10. The schematic for this design example is shown in Figure 51. Because the output current is 3 A, the ADP2303 is chosen for this application. Table 10. Step-Down DC-to-DC Regulator Requirements Parameter Input Voltage, VIN Output Voltage, VOUT Programmable UVLO Voltage PGOOD Specification 12.0 V 10% 3.3 V, 3 A, 1% VOUT ripple at full load condition VIN start-up voltage approximately 7.8 V Not used Additional Requirements None None None None The inductor peak current is calculated using the following equation: I PEAK = I LOAD(max) + where: ILOAD(max) = 3 A. IRIPPLE = 0.7 A. I RIPPLE 2 The calculated peak current for the inductor is 3.4 A. Therefore, in this application, select VLF10040T-4R7N5R4 as the inductor. OUTPUT CAPACITOR SELECTION Select the output capacitor based on the minimum output voltage ripple requirement, according to the following equation: 1 V RIPPLE = I RIPPLE x + ESR COUT 8x f xC sw OUT CATCH DIODE SELECTION Select the catch diode. A Schottky diode is recommended for best efficiency because it has a low forward voltage drop and faster switching speed. The average current of the catch diode in normal operation, with a typical Schottky diode forward voltage, can be calculated using the following equation: V + VD I DIODE( AVG ) = 1 - OUT V IN + V D x I LOAD(max) where: IRIPPLE = 0.7 A. fSW = 700 kHz. VRIPPLE = 33 mV (1% of output voltage). If ESR of the ceramic capacitor is 3 m, then COUT = 4 F. Because the output capacitor is one of two external components that control the loop stability and according to the recommended external components in Table 11, choose two 47 F capacitor with a 6.3 V voltage rating in this application. where: VOUT = 3.3 V. VIN = 12 V. ILOAD(max) = 3 A. VD = 0.4 V. Therefore, IDIODE(AVG) = 2.1 A. In this case, selecting a SSB43L, 4.0 A, 30 V surface-mount Schottky diode results in more reliable operation. RESISTIVE VOLTAGE DIVIDER SELECTION The output feedback resistive voltage divider is R VOUT = 0.800 V x 1 + TOP R BOT INDUCTOR SELECTION Select the inductor by using the following equation: L= For the 3.3 V output voltage, choose RTOP = 31.6 k and RBOT = 10.2 k as the feedback resistive voltage divider according to the recommended values in Table 11. The resistive voltage divider for the programmable VIN start-up voltage is 1. 2 V VSTARTUP = + 1.2 A x R EN1 + 1.2 V R EN2 (V IN - VOUT ) 0.3 x I LOAD (max) x f sw V + VD x OUT V +V D IN where: VOUT = 3.3 V. VIN = 12 V. ILOAD(max) = 3 A. VD = 0.4 V. fSW = 700 kHz. This results in L = 4.12 H. The closest standard value is 4.7 H; therefore, IRIPPLE = 0.7 A. If VSTARTUP = 7.8 V, choose REN2 = 10.2 k, and then calculate REN1, which, in this case, is 56 k. Rev. 0 | Page 20 of 28 ADP2302/ADP2303 VIN = 12V CIN 10F 25V REN1 56k 1% VIN RPGOOD 100k BST CBST 0.1F ADP2303 SW PGOOD VOUT = 3.3V 3A COUT1 47F 6.3V COUT2 47F 6.3V RTOP 31.6k 1% RBOT 10.2k 1% L D 4.7H SSB43L EN REN2 10.2k 1% GND FB 08833-049 Figure 51. Schematic for the Design Example Table 11. Recommended External Components for Typical Applications at 2 A/3 A Output Load Part Number ADP2302 VIN (V) 18 18 12 12 12 12 12 5 5 5 18 18 12 12 12 12 12 5 5 5 VOUT (V) 3.3 5.0 1.5 1.8 2.5 3.3 5.0 1.5 1.8 2.5 3.3 5.0 1.5 1.8 2.5 3.3 5.0 1.5 1.8 2.5 ILOAD(max) (A) 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 L (H) 6.8 10 4.7 4.7 4.7 6.8 6.8 3.3 3.3 3.3 4.7 6.8 2.5 3.3 3.3 4.7 4.7 2.2 2.2 2.2 COUT 2 x 22 F 2 x 22 F 2 x 47 F 3 x 22 F 3 x 22 F 2 x 22 F 2 x 22 F 2 x 47 F 2 x 47 F 2 x 22 F 2 x 47 F 47 F 3 x 47 F 3 x 47 F 2 x 47 F 2 x 47 F 47 F 3 x 47 F 3 x 47 F 3 x 47 F RTOP (k), 1% 31.6 52.3 10 12.7 21.5 31.6 52.3 10 12.7 21.5 31.6 52.3 10 12.7 21.5 31.6 52.3 10 12.7 21.5 RBOT (k), 1% 10.2 10 11.3 10.2 10.2 10.2 10 11.3 10.2 10.2 10.2 10 11.3 10.2 10.2 10.2 10 11.3 10.2 10.2 ADP2303 Rev. 0 | Page 21 of 28 ADP2302/ADP2303 CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential to obtaining the best performance for ADP2302/ADP2303. Poor layout can affect the regulation and stability, as well as the electromagnetic interface (EMI) and electromagnetic compatibility (EMC) performance. A PCB layout example is shown in Figure 53. Refer to the following guidelines for a good PCB layout: Place the input capacitor, the inductor, catch diode, output capacitor, and bootstrap capacitor close to the IC using short traces. Ensure that the high current loop traces are as short and wide as possible. The high current path is shown Figure 52. Maximize the size of ground metal on the component side to improve thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise on sensitive circuit nodes. VOUT INDUCTOR OUTPUT CAPACITORS GND BST CAP BST 1 INPUT CAPACITOR VIN 2 VIN EN 3 PGOOD 4 EXPOSED PAD 8 SW 7 GND 6 NC 5 FB 08833-051 Minimize the length of the FB trace connecting the top of the feedback resistive voltage divider to the output. In addition, keep these traces away from the high current traces and the switch node to avoid noise pickup. VIN BST ADP2302/ ADP2303 PGOOD SW EN GND FB 08833-050 Figure 52. Typical Application Circuit with High Current Lines Shown in Blue DIODE Figure 53. Recommended Layout for ADP2302/ADP2303 Rev. 0 | Page 22 of 28 ADP2302/ADP2303 TYPICAL APPLICATION CIRCUITS VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-052 08833-054 BST CBST 0.1F ADP2302ARDZ EN SW VOUT = 1.5V 2A COUT1 47F 6.3V COUT2 47F 6.3V RTOP 10k 1% RBOT 11.3k 1% L 4.7H D B330B Figure 54. ADP2302 Typical Application, VIN = 12 V, VOUT = 1.5 V, 2 A VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-053 08833-055 BST CBST 0.1F ADP2302ARDZ EN SW VOUT = 1.8V 2A COUT1 22F 6.3V COUT2 22F 6.3V COUT3 22F 6.3V RTOP 12.7k 1% RBOT 10.2k 1% L 4.7H D B330B Figure 55. ADP2302 Typical Application, VIN = 12 V, VOUT = 1.8 V, 2 A VIN = 12V VIN CIN 10F 25V BST CBST 0.1F ADP2302ARDZ-2.5 EN SW VOUT = 2.5V 2A COUT1 22F 6.3V COUT2 22F 6.3V COUT3 22F 6.3V L 4.7H D B330B PGOOD GND FB Figure 56. ADP2302 Typical Application, VIN = 12 V, VOUT = 2.5 V, 2 A VIN VIN CIN 10F 25V REN1 56k 1% RPGOOD 100k BST CBST 0.1F ADP2302ARDZ-3.3 SW PGOOD VOUT = 3.3V 2A COUT1 22F 6.3V COUT2 22F 6.3V L 6.8H D B330B EN REN2 10.2k 1% GND FB Figure 57. ADP2302 Typical Application, VIN = 12 V, VOUT = 3.3 V, 2 A, with Programmable 7.8 V UVLO Rev. 0 | Page 23 of 28 ADP2302/ADP2303 VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-056 BST CBST 0.1F ADP2302ARDZ-5.0 EN SW VOUT = 5.0V 2A COUT1 22F 16V COUT2 22F 16V L 6.8H D B330B Figure 58. ADP2302 Typical Application, VIN = 12 V, VOUT = 5 V, 2 A VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-057 08833-058 BST CBST 0.1F ADP2303ARDZ EN SW VOUT = 1.5V 3A COUT1 47F 6.3V COUT2 47F 6.3V COUT3 47F 6.3V RTOP 10k 1% RBOT 11.3k 1% L 2.5H D SSB43L Figure 59. ADP2303 Typical Application, VIN = 12 V, VOUT = 1.5 V, 3 A VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB RBOT 10.2k 1% BST CBST 0.1F ADP2303ARDZ EN SW VOUT = 1.8V 3A COUT1 47F 6.3V COUT2 47F 6.3V COUT3 47F 6.3V RTOP 12.7k 1% L 3.3H D SSB43L Figure 60. ADP2303 Typical Application, VIN = 12 V, VOUT = 1.8 V, 3 A VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-059 BST CBST 0.1F ADP2303ARDZ EN SW VOUT = 2.5V 3A COUT1 47F 6.3V COUT2 47F 6.3V RTOP 21.5k 1% RBOT 10.2k 1% L 3.3H D SSB43L Figure 61. ADP2303 Typical Application, VIN = 12 V, VOUT = 2.5 V, 3 A Rev. 0 | Page 24 of 28 ADP2302/ADP2303 VIN = 12V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-060 BST CBST 0.1F ADP2303ARDZ-5.0 EN SW VOUT = 5V 3A COUT1 47F 6.3V L 4.7H D SSB43L Figure 62. ADP2303 Typical Application, VIN = 12 V, VOUT = 5 V, 3 A VIN = 5V VIN CIN 10F 25V RPGOOD 100k PGOOD GND FB 08833-061 BST CBST 0.1F ADP2302ARDZ EN SW VOUT = 1.2V 2A COUT1 47F 6.3V COUT2 47F 6.3V RTOP 10k 1% RBOT 20k 1% L 3.3H D B330B Figure 63. ADP2302 Typical Application, VIN = 5V, VOUT = 1.2 V, 2 A Rev. 0 | Page 25 of 28 ADP2302/ADP2303 OUTLINE DIMENSIONS 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 8 1 5 4 2.29 (0.090) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 2.29 (0.090) TOP VIEW 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW 1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 1.65 (0.065) 1.25 (0.049) SEATING PLANE 0.51 (0.020) 0.31 (0.012) (PINS UP) 0.50 (0.020) 0.25 (0.010) 45 0.25 (0.0098) 0.17 (0.0067) 8 0 1.27 (0.050) 0.40 (0.016) COMPLIANT TO JEDEC STANDARDS MS-012-A A 072808A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 64. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 ADP2302ARDZ-R7 ADP2302ARDZ-2.5-R7 ADP2302ARDZ-3.3-R7 ADP2302ARDZ-5.0-R7 ADP2302-EVALZ ADP2303ARDZ-R7 ADP2303ARDZ-2.5-R7 ADP2303ARDZ-3.3-R7 ADP2303ARDZ-5.0-R7 ADP2303-EVALZ 1 Output Voltage Adjustable 2.5 V 3.3 V 5.0 V Adjustable 2.5 V 3.3 V 5.0 V Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP Evaluation Board 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP Evaluation Board Package Option RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 ADP2302/ADP2303 NOTES Rev. 0 | Page 27 of 28 ADP2302/ADP2303 NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08833-0-7/10(0) Rev. 0 | Page 28 of 28 |
Price & Availability of ADP2303ARDZ-25-R7
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